Job Summary

We are seeking an experienced SoC Architect with deep expertise in high-speed interface technologies including PCIe, CXL, and Network-on-Chip (NoC) architectures. The ideal candidate will lead the architectural definition, implementation strategy, and technical direction for next-generation semiconductor products, ensuring optimal system performance, power efficiency, and functionality.

Key Responsibilities

• Define and develop SoC architecture specifications with a focus on advanced interface technologies (PCIe Gen 5/6, CXL 2.0/3.0, custom NoC solutions)
• Create detailed micro-architectural specifications including block diagrams, interface definitions, and performance models
• Collaborate with IP teams to define and implement PCIe controllers, CXL interfaces, and custom NoC topologies
• Develop performance models and conduct analysis to optimize system throughput, latency, and power consumption
• Lead technical discussions with cross-functional teams including RTL designers, verification engineers, and physical design teams
• Identify architectural risks and develop mitigation strategies throughout the design lifecycle
• Evaluate and select third-party IP components when appropriate
• Participate in industry standard committees and stay current with emerging interface technologies
• Mentor junior architects and technical staff

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's or PhD preferred)
• At Least 8+ years of experience in SoC architecture with specific focus on high-speed interconnect technologies
• Deep technical knowledge of PCIe (Gen 4/5/6) and CXL specifications and implementations
• Extensive experience designing and implementing Network-on-Chip architectures
• Proficiency in SystemVerilog and UVM for architecture modeling and verification
• Strong understanding of SoC performance analysis and optimization techniques
• Experience with cache coherency protocols and memory subsystem design
• Demonstrated ability to lead complex architectural decisions and trade-offs

Preferred Qualifications

• Experience with PCIe and CXL switch design and implementation is an added advantage
• Experience with CXL 2.0/3.0 implementation and memory semantics
• Familiarity with emerging interface standards (UCIe, CCIX)
• Knowledge of AI/ML accelerator integration with high-speed interfaces
• Experience designing multi-die systems using advanced packaging technologies
• Expertise in power optimization techniques for complex SoCs
• Contribution to industry standards committees or publications
• Experience with high-performance computing, data center, or networking applications

Please refer to job description.